#ifndef __CORE_GCC_H__
#define __CORE_GCC_H__

#include "ch32v_def.h"
#include "core_riscv.h"

#ifndef __ASM
#define __ASM __asm__
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif


#ifndef FLASHSIZE_BASE
#define FLASHSIZE_BASE  0x1FFFF7E0UL
#endif

#ifndef UID_BASE
#define UID_BASE        0x1FFFF7E8UL
#endif

#ifndef OB_BASE
#define OB_BASE         0x1FFFF800UL
#endif

static __IO uint32_t PFIC_ISR1 = 0x0;
static __IO uint32_t PFIC_ISR2 = 0x0;


#ifndef CH32V3xx

 /**
  \brief   Enable IRQ Interrupts
  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __enable_irq(void)
{
  if (PFIC_ISR1 != 0 || PFIC_ISR2 != 0)
  {
    NVIC->IENR[0] = PFIC_ISR1;
    NVIC->IENR[1] = PFIC_ISR2;
  }
}

/**
  \brief   Disable IRQ Interrupts
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  PFIC_ISR1 |= (NVIC->ISR[0] & 0xFFFFF000);
  PFIC_ISR2 |= (NVIC->ISR[1] & 0x0FFFFFFF);

  NVIC->IRER[0] = 0xFFFFFFFF;
  NVIC->IRER[1] = 0xFFFFFFFF;
}

#endif // !RV_STATIC_INLINE


__STATIC_INLINE void HAL_NVIC_SystemReset(void)
{
  /* System Reset */
  NVIC_SystemReset();
}

#define  __set_FAULTMASK(f)  __disable_irq()

#endif // __CORE_GCC_H__